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Hybrid CMOS Single-Electron-Transistor Device and Circuit Design

Hybrid CMOS Single-Electron-Transistor Device and Circuit Design

Copyright: 2006
Pages: 238
ISBN: 9781596930704

Take advantage of the low-power consumption and enhanced functionality of SETs (single electron transistors) along with the high-speed driving and voltage gain of CMSO technology. This cutting-edge resource provides you with the conceptual framework for CMSO-SET hybrid circuit design. Supported with over 180 illustrations and packaged with a CD-ROM of practical supplementary material, the book explains spice simulation of SETs and co-simulation with CMOS, introduces specific design strategies for hybrid CMOS-SET circuits, and presents CMOS-SET co-fabrication techniques. You gain a thorough understanding of the pros and cons of digital SETs, learn how SETs can help to solve the intrinsic drawbacks of CMOS technology, and discover how the hybridization of both technologies can produce new analog functionalities which are difficult to achieve in a pure CMOS approach. From the basic physics of single electron transistors and SET modeling, to advanced concepts like CMSO-SET co-integration, the book helps you realize significant performance benefits by showing you how to incorporate SET technology into your design projects.
Preface.; Introduction: CMOS Scaling and Single Electronics - CMOS Scaling Limits. Emerging Nanotechnologies: Life After CMOS. Single Electron Transistor: An Overview. Short History.; Compact Modeling of Single Electron Transistors - CAD Tools for SET Simulation. Orthodox Theory of Single Electron Tunneling. Carrier Transport in SET. Compact Modeling of SET. Model Verification. Subthreshold Slope. Parameter Extraction. Other SET Models. SET and MOSFET Modeling Techniques: A Comparison.; Single Electron Transistor Logic - Single Electron Memory Versus Logic. SET Inverter Characteristics. Analysis of Inverter Characteristics. Propagation Delay of SET Inverter. Other Single Electron Logic Gates. Comparison between SET and CMOS Logic.; Hybridization of CMOS and SET - Motivation for CMOS-SET Hybridization. Challenges for CMOS-SET Hybridization. CMOS-SET Co-Simulation and Co-Design. Case Studies of Different Hybrid CMOS-SET Architectures. SETMOS: Coulomb Blockade Oscillations at Micro Ampere Range.; Few Electron Multiple Value Logic and Memory Design -Multiple Value Switching Algebra. Motivation for MV Logic Design. Challenges for MV Logic Circuit Design. SETMOS Quaternary Logic. SETMOS Quaternary SRAM.; Fabrication of Single Electron Transistors and Compatibility with Silicon CMOS - Challenges of Single Electron Transistor Fabrication. Single-Island SET Fabrication. Fabrication of Multi-Island SET. Fabrication of Carbon Nanotube and Molecular SET.; Appendixes A and B.;
  • Adrian M. Ionescu Adrian Mihai Ionescu is head of the Laboratory of Micro/Nanoelectronic Devices and an associate professor at the Swiss Federal Institute of Technology, Lausanne, Switzerland. He has served in the technical program committees of the IEEE International Electron Device Meeting, the IEEE International Symposium on Quality Electronic Design and the International Micro- and Nano-Engineering Conference. Additionally, he served as Technical Program Chair of the 36th European Solid-State Device Research Conference (ESSDERC 2006). The author of more than 100 research papers, Dr. Ionescu received a Ph.D. in microelectronics from the University Politechnica Bucharest, Romania and a Ph.D. in physics of semiconductor devices from the Institut National Polytechnique de Grenoble, France.
  • Santanu Mahapatra Santanu Mahapatra is an assistant professor in the Center for Electronics Design and Technology at the Indian Institute of Science, Bangalore, India. Dr. Mahapatra has published several research papers in international journals and major conferences. He received his Ph.D. from the Swiss Federal Institute of Technology, Lausanne.
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