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Introduction to DNA Self-Assembled Computer Design

Introduction to DNA Self-Assembled Computer Design

Copyright: 2007
Pages: 230
ISBN: 9781596931688

Print Book $105.00 Qty:
Here's a trail-blazing resource that details microchip fabrication using bottom-up DNA self-assembly. This unique book provides a theoretical and practical bridge from today's chip technology to the molecular-scale circuitries that lie ahead. It connects familiar semiconductor concepts to the latest breakthroughs in the use of DNA as construction material, and maps out a detailed method for developing DNA self-assembled computer systems that features case study designs of lightweight self-organizing computer architectures. Probing both the science and the engineering involved, this one-of-a-kind resource reviews current microchip fabrication methods and architectures and discusses fundamentals of nanoscale design and DNA self-assembly. The book addresses self-assembled circuitry and design issues in depth, explaining DNA scaffolding structures and providing techniques for organizing molecular-scale materials, circuits and architectures. This cutting-edge volume explores current technology limitations involving small scale control and large scale randomness, along with architectural challenges to node design, routing, and interfacing to the microscale. You also find case studies of a nanoscale active network architecture and a self-organizing SIMD architecture that give you a clear look at self-assembled system design pointing the way forward. Concluding with a digest of current practices in DNA nanostructure synthesis and insights into the revolutionary design, fabrication, and operational paradigms raised by the concept of self assembly, this roadmap to DNA microchip synthesis is indispensable for your work in researching and developing nanoscale computer structures, devices, and applications.
Introduction - Current Fabrication Methods. Current Devices. Current Architectures. Nanoscale Devices and Interconnect. Summary. ; DNA Self-Assembly - Nucleotides, Oligos, and the Double Helix. DNA Geometries and Motifs. Thermodynamics and Sequence Design. Metrics and Design Rules. Hierarchical Assembly. Summary. ; Self-Assembled Circuitry and Design -Introduction. Related Work. DNA Scaffolding Structures. DNA-Guided Self-Assembly. Design Tool Flow. Summary. ; Technological Implications and Architectural Challenges - Technology Limitations. Architectural Challenges. Summary. A Nanoscale Active Network Architecture - System Model. Execution Model. Instruction Set and Packet Formats. Interconnection Network Finding Resources. Memory. Interfacing Execution and Memory. Summary. ; A Self-Organizing Defect Tolerant SIMD Architecture - System Overview. Node Microarchitecture. System Configuration. System Architecture. Performance Evaluation. Summary. ; Temporal Aspects of Computing -Introduction. Pre-Fabrication (Design-Time Computation). At-Fabrication (Build-Time Computation). Postfabrication (Run-Time Computation). Generalizations. Summary. ; At-Fabrication Computing (or Build-Time Computation) -Introduction. Related Work. Oracles. Decoupled Array Multiprocessor. Summary. Next Steps and Concluding Remarks Appendix: Current Practices in DNA Nanostructure Synthesis ;
  • Christopher Dwyer Christopher Dwyer is an assistant professor in the Electrical and Computer Engineering Department at Duke University. He was general co-chair of the 2006 IEEE Nano-nets Conference and program chair of the 4th Workshop on Non-Silicon Computing (2007). He has served as guest editor for IEEE Transactions on Nanotechnology and the ACM Journal on Emerging Technologies in Computing Systems, and has authored or co-authored over 35 papers on topics in self-assembling computer architecture, nanoscale system design and simulation, DNA-guided self-assembly, and self-assembling device fabrication. He received his Ph.D. in computer science from the University of North Carolina.
  • Alvin Lebeck Alvin Lebeck is a professor in the Computer Science Department at Duke University. He is also associate editor of the Journal of Instruction-Level Parallelism and was technical program co-chair of the 1st International Conference on Nano-Networks (2006). He has written or co-written numerous journal articles and conference papers on topics in computer architecture, nano-scale systems, memory system, energy efficient computing, and multiprocessors. He earned his Ph.D. at the University of Wisconsin at Madison.
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