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Wafer-Level Testing and Test During Burn-In for Integrated Circuits

Wafer-Level Testing and Test During Burn-In for Integrated Circuits

By (author): Sudarshan Bahukudumbi
Copyright: 2010
Pages: 210
ISBN: 9781596939905

eBook $109.00 Qty:
Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing. Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constraints. Moreover, this unique book helps practitioners address the issue of enabling next generation products with previous generation testers. Practitioners also find expert insights on current industry trends in WLTBI test solutions.
Introduction - Background. Key Drivers for Wafer-Level Test and Burn-In. Wafer-Level Test Planning for Core-Based SoCs. Wafer-Level Defect Screening for Mixed-Signal SoCs. WLTBI of Core-Based SoCs. Power Management for WLTBI. How This Book Is Organized. ; Wafer-Level Test and Burn-In: Industry Practices and Trends - Overview and Defnitions. Status of Wafer-Level Test and WLBI. Doing Both Wafer-Level Test and Wafer-Level Burn-In. Practical Matters. Future Projections.; Resource-Constrained Testing of Core-Based SoCs - Defect Probability Estimation for Embedded Cores. Test-Length Selection for Wafer-Level Test. Experimental Results. Test Data Serialization. Summary.; Defect Screening for Big-D/Small-AĆ¹ Mixed-Signal SoCs - Test Wrapper for Analog Cores. Wafer-Level Defect Screening: Mixed-Signal Cores. Generic Cost Model. Cost Model: Quantitative Analysis. Summary. Acknowledgments.; Wafer-Level Test During Burn-In: Test Scheduling for Core-Based SOCs - Cycle-Accurate Power Modeling. Test Scheduling for WLTBI. Heuristic Procedure to Solve PCore Order. Baseline Methods. Experimental Results. Summary. Acknowledgments.; Wafer-Level Test During Burn-In: Power Management by Test-Pattern Ordering - Background: Cycle-Accurate Power Modeling. Test-Pattern Ordering Problem: PTPO. Heuristic Methods for Test-Pattern Ordering. Baseline Approaches. Experimental Results. Summary.; Wafer-Level Test During Burn-In: Power Management by Test-Pattern Manipulation - Minimum-Variation X-Fill Problem: PMV F. Framework to Control Power Variation for WLTBI. Baseline Approaches. Experimental Results. Summary.; Conclusions - Summary. Future Work. List of Symbols. List of Acronyms. About the Authors. Index.;
  • Sudarshan Bahukudumbi Sudarshan Bahukudumbi is a quality and reliability test engineer at Intel Corporation. He has written several articles in peer-reviewed journals and is a frequent presenter at industry conferences. He holds an M.S. and Ph.D. in electrical engineering from New Mexico University and Duke University, respectively.
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