Description
Here is the first book to propose HTS as a complete, more effective design approach. The author explains how HTS, unlike most existing high-level synthesis techniques that optimize the circuit architecture for area and performance only, is able to explore the synthesis freedom provided at high level to derive an inherently testable architecture at low or even no overhead. By permitting testing from the earliest design stages to minimize or even eliminate serious testing problems, HTS boosts design quality and shortens the development cycle. The book provides an introduction to HTS and helps you develop a comprehensive understanding of this emerging technology by presenting: The background of HTS terminology, operation scheduling, and resource allocation algorithms used in high-level synthesis; A discussion of various HTS techniques for both scan and built-in self-test methodologies; Coverage of register-transfer level test synthesis; A self-contained introduction to high-level synthesis algorithms and digital testing; Examples of several effective HTS schemes for highly testable digital circuits, assumingnon-scan or partial-scan test strategies; A current survey of representative HTS systems. For VLSI engineers and developers involved in design-for-test methodology and CAD tool development, this pioneering work provides a first look at the promising HTS technology. It also is a highly informative reference for industry and academic researchers and graduate students interested in this new area.
Table Of Contents
1.Introduction: Circuit Testing. High-Level Synthesis in VLSI Design. High-Level Test Synthesis. Contribution and Overview. 2. Background: Behavioral Modeling. Operation Scheduling. Variable Lifetime. Resource Allocation. High-Level Synthesis Flow. Testability Analysis. Brief Review of High-Level Test Synthesis. ; 3. Sequential Depth Reduction During Allocation: Controllability and Observability Enhancement. Sequential Depth Reduction. Implementation. Experimental Results. ; 4. Sequential Loop Reduction During Allocation: Effect of Sequential Loops on Testability. Implementation. Experimental Results. ; 5. Testability Synthesis During Scheduling: Scheduling for Controllability/Observability Enhancement. Scheduling for Sequential Depth/Loop Reduction. Implementation. Experimental Results. ; 6. Conditional Resource Sharing for Testability: Hierarchical Control-Data Flow Graph. Effect of Conditional Resource Sharing. A Conditional Resource Sharing Method for HTS. Experimental Results. ; 7. State-of-the-Art High-Level Test Synthesis: Synthesis for Built-In Self Test. Synthesis for Scan Path and Test Point Insertion. Test Synthesis at RT Level.;
Author
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Mike Tien-Chien Lee
Dr. Mike Tien-Chien Lee is a software engineer at Avant! Corp. He holds a Ph.D. in electrical engineering from Princeton University. Dr. Lee serves on program committees of IEEE International Test Synthesis Workshop. He received Best Paper Awards at the Asia and South Pacific Design Automation Conference (ASP-DAC) in 1995, and the IEEE/ACM Design Automation Conference (DAC) in 1996.