Make way for solutions to the challenges in chip reliability, power delivery, I/O signaling, and heat removal now blocking the way to ultimate performance 3D gigascale SoC. This cutting-edge book on off-chip technologies puts the hottest breakthroughs in high-density compliant electrical interconnects, nanophotonics, and microfluidics at your fingertips, integrating the full range of mathematics, physics, and technology issues together in a single comprehensive source. You get full details on state-of-the-art I/O interconnects and packaging, including mechanically compliant I/O approaches, fabrication, and assembly, followed by the latest advances and applications in power delivery design, analysis, and modeling. The book explores interconnect structures, materials, and packages for achieving high-bandwidth off-chip electrical communication, including optical interconnects and chip-to-chip signaling approaches, and brings you up to speed on CMOS integrated optical devices, 3D integration, wafer stacking technology, and through-wafer interconnects. The volume spells out the latest heat removal technologies including chip-scale microchannel cooling, integrated micropumps and fluidic channels, and various types of carbon nanotube interconnects, along with coverage of wafer-level testing and probe substrates that features probe modules for testing GSI chips. Supported by 100 illustrations and featuring up-to-date physical models and experimental research in all I/O interconnect technologies essential to 3D GSI/TSI realization, this groundbreaking book offers practical guidance to help you achieve next-generation system-on-a-chip performance.
Table Of Contents
Introduction: The Interconnect Problem. Die-Package Interaction and Impact on Low-k ILD. Mechanically Compliant I/O Interconnects and Packaging. Power Delivery Design and Analysis. Challenges for Off-chip Signaling & Communication. Optical Interconnects and Various Approaches for Chip-to-Chip Signaling. CMOS Integrated Optical Devices. 3D Integration and Wafer Stacking Technology. Through-Wafer Interconnects. Limits of Current Heat Removal Technology & Opportunities. Chip-Scale Microchannel Cooling Planar and Vertical. Integrated Micropumps and Fluidic Channels. CNT Thermal Properties & Applications for Heat Removal. Wafer-Level Testing and Probe Substrates. The Convergence of Semiconductor Technology and the Life Sciences.; To view complete TOC:; Click Google Preview button under book title above, then click on Contents tab.;