Description
Phase Locked Loop Frequency Synthesis Methods introduces an efficient, modern approach to PLL frequency synthesis using multifrequency phase detection (MFPD) and phase-domain synthesis methodologies. These techniques deliver both exceptional high spectral purity and necessary fast frequency agility within a compact, single-loop architecture. This specialized text provides a streamlined path to smaller, cleaner, and more reliable synthesizer designs, effectively eliminating the traditional divider-ratio limits and bottlenecks inherent in older constructs.
Bridge theoretical concepts to direct hardware implementation with practical, bench-ready methods. Learn how to apply MFPD for effective suppression of fractional spurs and fundamental phase noise. Detailed analysis reveals how PDS and advanced PDS-DSM architectures deliver rapid lock times and fine resolution within a single loop. Practitioners gain the insight necessary to understand the tradeoffs between integer-N, fractional-N, DDS-assisted, and MFPD-based topologies, enabling the immediate selection and optimization required for stringent performance requirements. Master design methods to tune loop parameters, choose components, and manage power budgets to meet the most demanding spectral masks.
Supported by 56 detailed illustrations, more than 50 equations, and clear performance comparisons, this is an essential tool for RF, microwave, and systems engineers developing sophisticated local oscillators and synthesizers. The implementation-focused material offers the guidance required for high-stakes applications in communications, radar, electronic warfare, and instrumentation systems. Real-world examples demonstrate how each technique performs under practical constraints, empowering professionals to cut parts count, reduce overall system complexity, and move confidently from design theory to fully realized hardware.
Table Of Contents
Preface
Introduction
1. Schemes with dividers of integer variable division ratios
1.1. The simplest one-loop structure
1.2. Scheme with a frequency mixer
1.3. Tollefson’s scheme
1.4. Martin’s scheme
1.5. Cascade PLL synthesizer
1.6. Three-loop scheme
1.7. Thrower’s scheme
2. Other schemes
2.1. Chenakin’s scheme
2.2. Gorevoy’s synthesizer
2.3. Scheme with DDS in PLL
2.4. Sadowski’s scheme
2.5. Extending the frequency range
3. Schemes with fractional divider and with suppression of fractional noise, and other schemes
3.1. Braymer’s-Gilletter’s scheme
3.2. Integrator option
3.3. Cox’s scheme
3.4. Underwood’s scheme
3.5. Variant with pulse PD of “sampling-storage” type
3.6. Nikiforov’s scheme
3.7. Koslov’s scheme
3.8. Simplified version of Direct Digital Synthesizer
4. The idea of a Multi-Frequency Phase Detector (MFPD)
4.1. Idea by Bosselaers
4.2. Improvement of the Bosselaers’s scheme
4.3. Variant with accumulator and RS flip-flop
4.4. Variant with Ring Register
5. Synthesizers of PDS and PDS-DSM types
5.1. Idea of Phase Splitting
5.2. Prerequisites for using the idea
5.3. MFPD in versions for PDS and PDS-DSM synthesizers
5.4. Phase splitters
5.5 Phase splitter onlogic elements
5.6. Static characteristics of MFPD
5.7. The operation area of the static characteristics of the MFPD
5.8. Signal spectrums of synthesizers of PDS and PDS-DSM types
5.9. Reduction of power consumption
5.10. Comparison of spectrums of PDS, PDS-DSM, and Fractional-N PLL synthesizers
5.11. About the number of split phases
Note
Conclusion
References